1. Field of the Invention
The present invention relates to a liquid crystal display device using poly-silicon, and more particularly to a liquid crystal display device and a fabricating method thereof that reduce the number of processes and production cost.
2. Discussion of the Related Art
Silicon is divided into two main classes of amorphous silicon and crystalline silicon in accordance with crystallization state.
Amorphous silicon can be deposited into a thin film at a low temperature below 350° C. Because of this, amorphous silicon is mainly used for thin film transistors of liquid crystal display devices. However, it is difficult to apply amorphous silicon to a large-size liquid crystal display device that requires an excellent electrical characteristic due to its low mobility below 0.5 cm2/Vs.
When compared with amorphous silicon, poly-silicon (crystalline silicon) has a high mobility of several tens to hundreds of cm2/Vs. Thus, there has been active research on high-density and large-size liquid crystal display (LCD) devices by applying poly-silicon to the semiconductor layer of the thin film transistors (TFT) of the LCD devices. In particular, when the poly-silicon TFTs are applied to a liquid crystal display panel, the TFTs of the screen area and the driving circuits can be fabricated or integrated together on the same substrate.
In general, the electrical properties of poly-silicon depend on the size of its crystal grain. That is, the bigger the size of crystal grain is, the higher the mobility of poly-silicon is.
Such a poly-silicon layer can be formed with various methods. It can be directly deposited on a substrate, or it can be formed by crystallizing amorphous silicon which is deposited on a substrate. Plasma enhanced chemical vapor deposition (PECVD) method is generally used to directly deposit poly-silicon on a substrate in which poly-silicon is deposited using a mixture gas of SiF4, SiH4 and H2 at a deposition temperature above 400° C. Due to the difficulty of controlling the crystal grain, this direct-depositing method is not preferred for an actual liquid crystal display device. The methods of crystallizing amorphous silicon into poly-silicon includes solid phase crystallization (SPC) in which amorphous silicon that is deposited on a substrate is heated in a furnace and is then crystallized, and a method in which amorphous silicon that is deposited on a substrate is irradiated by an excimer laser and is then crystallized. The crystallizing method using an excimer laser is mainly used to form a poly-silicon layer in an LCD device because its process temperature is low and it is relatively easy to control the crystal grain.
Recently, a new crystallizing process called sequential lateral solidification (hereinafter ‘SLS’) has been introduced in the industry in which an excimer laser is irradiated on an amorphous silicon thin film to completely melt the thin film, and then the crystals of the thin film grow vertically from the side surface. This SLS technique is disclosed in International Patent No. WO 97/45827 and Korea Patent Publication (Laid-Open) No. 2001-004129.
FIGS. 1 and 2 represent a related art poly-silicon TFT in a liquid crystal display device.
Referring to FIGS. 1 and 2, the poly-silicon TFT of the liquid crystal display device (top-gate type) includes a gate electrode 6 connected to a gate line 2, a source electrode 8 connected to the data line 4, a drain electrode connected to a pixel electrode 22, and an active layer 14 to form a channel in response to a control signal applied to the gate electrode 6.
The active layer 14 includes a channel area 14C, a source area 14S, a drain area 14D and a lightly doped drain (herein after ‘LDD’) area 14L, wherein the channel area 14C is a poly-silicon layer formed on a buffer film 16, overlaps the gate electrode 6, and is not doped with impurities. When the poly-silicon TFT is N-type, the source area 14S and the drain area 14D are doped with n+ ions, and the LDD area 14L is doped with n− ions. The LDD area 14L is located between the channel area 14C and the source area 14S and between the channel area 14C and the drain area 14D to reduce the off-current of the poly-silicon TFT.
The gate electrode 6 overlaps the channel area 14C of the active layer 14 with a gate insulating film 12 therebetween, and forms a channel through which electric currents flow between the source electrode 8 and the drain electrode 10 in response to a scan voltage supplied from the gate line 2. The source electrode 8 is connected to the source area 14S of the active layer 14 through a source contact hole 24S that runs through the gate insulating film 12 and an interlayer insulating film 26. The drain electrode 14D is connected to the drain area 14D of the active layer 14 through a drain contact hole 24D that runs through the gate insulating film 12 and the interlayer insulating film 26.
The poly-silicon TFT supplies a data voltage of the data line 4 to the pixel electrode 22 connected to the drain electrode 10, in response to a scan pulse from the gate line 2.
An aligning mark 28 is formed at four edges of the substrate of the liquid crystal display device. The aligning mark 28 is used to align the masks in the fabricating process. The aligning mark 28 is formed with a semiconductor layer along with the active layer 14 at the same time.
FIGS. 3A to 3F illustrate a fabricating method of the liquid crystal display device.
Referring to FIG. 3A, a buffer film 16 is formed by depositing an insulating material such as SiO2 or SiNx on the entire surface of a lower substrate 1. An amorphous silicon layer is deposited on the entire surface of the buffer film 16. Hydrogen contained in the amorphous silicon layer is removed through a dehydrogenation process in which the amorphous silicon layer is heated at about 400° C. After the dehydrogenation process, the amorphous silicon layer is crystallized by a laser annealing into a poly-silicon layer.
Referring to FIG. 4A, when the SLS method is used for the laser crystallization process, a mask 41 is aligned on the amorphous silicon layer 43. The mask 41 includes a transmitting pattern 41a and a shielding pattern 41b, wherein the transmitting pattern 41a transmits laser beam 42 and the shielding pattern 41b blocks the laser beam 42. The laser beam 42 is irradiated on the amorphous silicon layer 43 through the mask 41. Then, the amorphous silicon layer 43 exposed to the laser beam 42 through the transmitting pattern 41a of the mask 41 is melted. The amorphous silicon layer 43 on which the laser beams 42 are irradiated is melted down to reach the interface that is in contact with the buffer film 16. The amorphous silicon layer 43 melted in this way becomes crystallized as its temperature becomes lower. Crystallization is induced from seeds that exist at the side surface that is in contact with the adjacent amorphous silicon layer 43, which is in a solid state. Through this crystallization process, the amorphous silicon layer 43 irradiated by the laser beams 42 transforms into a poly-silicon layer 44 as illustrated in FIGS. 4A and 5A. Subsequently, at least one of the mask 41 and the substrate 1 moves to align the transmitting pattern 41a of the mask 41 to the amorphous silicon layer 43 that has not been crystallized. Then, the laser beam 42 is irradiated on the amorphous silicon layer 43 through the moved mask 41. After the rest of the amorphous silicon layer 43 is melted, crystallization again proceeds from the seeds existing at the side surface, i.e., the interface with the poly-silicon layer 44, as its temperature becomes lower. The entire surface or part of the amorphous semiconductor layer 43 is crystallized to become the poly-silicon layer 44 through two repetitions of such an exposure process, as illustrated in FIGS. 4B and 5B.
Referring to FIG. 6A, a photo-resist 47 is spread over the entire surface of the poly-silicon layer 44. A mask 45 is aligned on the photo-resist 47 for patterning. The mask 45 has a transmitting pattern 45a and a shielding pattern 45b, wherein the transmitting pattern 45a is for defining the active area and the aligning mark by transmitting the laser beam 46, and the shielding pattern 45b is for blocking the laser beam 46. After the photo-resist 47 is developed as in FIG. 6B, the poly-silicon layer 44 is dry-etched through the remaining pattern of the photo-resist 47. After the dry-etch process, when the remaining patterns of the photo-resist 47 are removed by a stripping process, the pattern of the active layer 14 and the aligning mark 28 are formed on the substrate 1, as illustrated in FIG. 3A.
FIG. 7 summarizes a process sequence from the buffer layer 16 to the active layer 14 and the aligning mark 28. The process sequence includes the following steps in order: a deposition process of the buffer layer 16 (step S11), a deposition process of the amorphous silicon layer 43 (step S12), a dehydrogenation process (step S13), a laser crystallization process (step S14), a photolithography process for defining the active layer 14 and the aligning mark 28, which includes a photo-resist spreading process, an exposure process and a development process (step S15), an etching process of the poly-silicon layer 44 (step S16), and removing process of the photo-resist (step S17).
Referring to FIG. 3B, an insulating material such as SiO2 or SiNx is deposited on the entire surface of the buffer layer 16 on which the active layer 14 and the aligning mark 28 have been formed, thereby forming a gate insulating film 12. A gate metal layer such as aluminum and aluminum/neodymium is deposited on the entire surface of the lower substrate 1 where the gate insulating film 12 has been formed. The mask for defining the gate metal patterns is aligned on the gate metal layer. And, the gate metal layer is patterned by performing another photolithography process including a spreading process, an exposure process and a development process of a photo-resist, an etching process and a removing process of the photo-resist. As a result, a gate electrode 6 of the poly-silicon TFT, a gate line 2 and a gate pad (not shown) are formed on the gate insulating film 12.
When the gate electrode 6 is formed in this way, n− ions are injected into the active layer 14 using the gate electrode 6 as a mask. Then, the LDD area 14L is formed at both sides of the active layer 14C of pure poly-silicon that overlaps the gate electrode 6.
Referring to FIG. 3C, a photo-resist (not shown) is spread on the entire surface of the lower substrate 1 where the gate metal patterns have been formed. A mask is aligned on the photo-resist to define a source area 14S and a drain area 14D of the active layer 14. The photo-resist patterns are formed on the lower substrate 1 by an exposure and development process, with the photo-resist patterns exposing the source area 14S and the drain area 14D of the active layer 14. n+ ions are then injected into the source area 14S and the drain area 14D of the active layer 14 with the photo-resist patterns.
Referring to FIG. 3D, an insulating material such as SiO2 or SiNx is deposited on the entire surface of the gate insulating film 12, thereby forming an interlayer insulating film 26 on the gate insulating film 12. A photo-resist (not shown) is spread on the entire surface of the interlayer insulating film 26. And, a mask is aligned on the photo-resist to define a source contact hole 24S and a drain contact hole 24D. The photo-resist patterns are formed on the interlayer insulating film 26 through an exposure and development process. The interlayer insulating film 26 and the gate insulating film 12 are etched with the photo-resist patterns. As a result, the source contact hole 24S and the drain contact hole 24D that run through the interlayer insulating film 26 and the gate insulating film 12 are formed, with the source area 14S and the drain area 14D of the active layer 14 being exposed.
Referring to FIGS. 3E and 3F, a metal layer is deposited on the entire surface of the interlayer insulating film 26 where the source contact hole 24S and the drain contact hole 24D have been formed. A photo-resist (not shown) is spread on the entire surface of the metal layer. And, a mask is aligned on the photo-resist to define a source electrode 8 and a drain electrode 10. The photo-resist patterns are formed on the metal layer by an exposure and development process. The metal layer is etched with the photo-resist patterns, and the photo-resist patterns are removed. As a result, the source electrode 8 and drain electrode 4 are formed on the lower substrate 1, along with a data line 4 and data pads (not shown) at the same time. The source electrode 8 is connected to the source area 14S of the active layer 14 through the source contact hole 24S. The drain electrode 10 is connected to the drain area 14D of the active layer 14 through the drain contact hole 24D. An inorganic or organic insulating material is formed on the entire surface of the interlayer insulating film 26 where the source electrode 8 and the drain electrode 10 have been formed in this way, thereby forming a protective film 18. A photo-resist (not shown) is spread on the entire surface of the protective film 18. And, a mask is aligned on the photo-resist to define a pixel contact hole 20. The photo-resist patterns are formed on the protective film 18 through an exposure and development process. The protective film 18 is etched with the photo-resist patterns. As a result, the pixel contact hole 20 that runs through the protective film 18 is formed, with part of the drain electrode 10 being exposed.
A transparent conductive material, for example, ITO is deposited on the entire surface of the protective film where the pixel contact hole 20 has been formed. A photo-resist (not shown) is spread on the entire surface of the transparent conductive material layer. And, a mask is aligned on the photo-resist to define the pixel electrode 22 (See FIG. 2). The photo-resist patterns are formed on the transparent conductive material layer by an exposure and development process. The transparent conductive material layer is etched with the photo-resist patterns. As a result, the pixel electrode 22 connected to the drain electrode 10 through the pixel contact hole 20 is formed, as illustrated in FIGS. 1 and 2.
However, the fabricating method of the poly-silicon TFT of the related art, as described above, is disadvantageous in that it requires a large number of processes and a long time, and that materials such as photo-resist are wasted. Also, due to such problems, the production cost is high.